An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs.
Chaoyang ZhuKejie HuangShuyuan YangZiqi ZhuHejia ZhangHaibin ShenPublished in: CoRR (2020)
Keyphrases
- field programmable gate array
- convolutional neural networks
- hardware implementation
- embedded systems
- parallel computing
- hardware software
- programmable logic
- hardware architecture
- hardware design
- fpga implementation
- hardware and software
- computing systems
- fpga technology
- digital signal processing
- low cost
- real world
- convolutional network
- sparse data
- image processing algorithms
- high dimensional
- parallel architectures
- real time
- image processing
- compressed sensing
- massively parallel
- structured data
- processing units
- application specific integrated circuits
- general purpose processors
- data sets