A power-efficient FPGA accelerator: Systolic array with cache-coherent interface for pair-HMM algorithm.
Megumi ItoMoriyoshi OharaPublished in: COOL Chips (2016)
Keyphrases
- systolic array
- computationally efficient
- single pass
- learning algorithm
- hardware implementation
- dynamic programming
- forward backward
- optimal solution
- database
- detection algorithm
- computational complexity
- objective function
- similarity measure
- hit rate
- parallel implementation
- agent architecture
- low cost
- efficient implementation
- expectation maximization
- np hard
- user interface
- pairwise
- databases