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Divide and concatenate: a scalable hardware architecture for universal MAC.

Bo YangRamesh KarriDavid A. McGrew
Published in: FPGA (2004)
Keyphrases
  • hardware architecture
  • hardware implementation
  • hardware architectures
  • field programmable gate array
  • associative memory
  • signal processing
  • efficient implementation
  • real time
  • feature space
  • query processing