Modeling and design of a dual-residue pipelined ADC in 130nm CMOS.

Eirik Steen-Hansen Trond Ytterdal

Published in: NORCHIP (2012)

Keyphrases

circuit design
single chip
analog to digital converter
high speed
design process
low power
low cost
power consumption
modeling method
software architecture
modeling language
design considerations
cmos technology