Low power and area efficient error tolerant adder for image processing application.
M. PriyadharshniSundaram KumaravelPublished in: Int. J. Circuit Theory Appl. (2020)
Keyphrases
- low power
- error tolerant
- image processing
- power consumption
- low cost
- high speed
- logic circuits
- digital signal processing
- signal processing
- subgraph isomorphism
- ultra low power
- real time
- vlsi circuits
- power reduction
- cmos technology
- single chip
- image sensor
- graph matching
- image registration
- pattern recognition
- feature extraction
- neural network