Reusability-aware cache memory sharing for chip multiprocessors with private L2 caches.
Hyunhee KimSungjune YounJihong KimPublished in: J. Syst. Archit. (2009)
Keyphrases
- memory access
- multithreading
- shared memory
- cache misses
- memory hierarchy
- data access
- main memory
- memory subsystem
- parallel computing
- memory management
- random access memory
- access latency
- shared memory multiprocessors
- distributed memory
- computational power
- external memory
- message passing
- memory bandwidth
- data sharing
- highly efficient
- instruction set
- privacy preserving
- parallel algorithm
- information sharing
- access patterns
- parallel implementation
- parallel architecture
- parallel programming
- processor core
- learning objects
- secondary storage
- data structure
- memory space
- computing power
- low cost
- hardware implementation
- memory requirements
- index structure
- operating system
- e learning
- speculative execution