DSP and ASIC implementation of a channel filter for a 3G UTRA-TDD system.
Ronny VeljanovskiJugdutt SinghMichael FaulknerPublished in: PIMRC (2002)
Keyphrases
- hardware implementation
- hardware architecture
- design methodology
- high speed
- signal processing
- impulse response
- median filter
- texas instruments
- neural network
- systolic array
- digital signal processing
- circuit design
- communication channels
- application specific
- noise reduction
- efficient implementation
- computer simulation
- artificial intelligence