A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes.
Hidehiro ShigaDaisaburo TakashimaShinichiro ShiratakeKatsuhiko HoyaTadashi MiyakawaRyu OgiwaraRyo FukudaRyosuke TakizawaKosuke HatsudaFumiyoshi MatsuokaYasushi NagadomiDaisuke HashimotoHisaaki NishimuraTakeshi HiokaSumiko M. DoumaeShoichi ShimizuMitsumo KawanoToyoki TaguchiYohji WatanabeShuso FujiiTohru OzakiHiroyuki KanayaYoshinori KumuraYoshiro ShimojoYuki YamadaYoshihiro MinamiSusumu ShutoKoji YamakawaSoichi YamazakiIwao KunishimaTakeshi HamamotoAkihiro NitayamaTohru FuruyamaPublished in: IEEE J. Solid State Circuits (2010)