3-channel area-optimized ΣΔ ADC in 0.16-µm CMOS with 20-kHz BW and 86-dB DR.

Fabio Sebastiano Robert H. M. van Veldhoven

Published in: ESSCIRC (2013)

Keyphrases

analog to digital converter
power consumption
high speed
multi channel
single chip
low cost
low power
circuit design
power supply
database
sampling rate
real time
communication channels
wireless channels
focal plane
low voltage