Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links.
Sebastian WernerJavier NavaridasMikel LujánPublished in: HPCA (2017)
Keyphrases
- low latency
- low power
- high speed
- high bandwidth
- single chip
- image sensor
- low cost
- focal plane
- low power consumption
- highly efficient
- real time
- mixed signal
- digital signal processing
- data acquisition
- power consumption
- virtual machine
- cmos technology
- signal processor
- network structure
- power reduction
- low voltage
- power dissipation
- printed circuit boards
- logic circuits
- mobile phone
- energy consumption
- high throughput