Model Checking a Logic over Systems with Regular Sets of Processes.
Anantha PadmanabhaR. RamanujamPublished in: DIAS/EDUDM@ISEC (2017)
Keyphrases
- model checking
- asynchronous circuits
- automated verification
- temporal logic
- finite state machines
- model checker
- epistemic logic
- verification method
- bounded model checking
- alternating time temporal logic
- modal logic
- formal methods
- linear temporal logic
- formal verification
- reactive systems
- process algebra
- timed automata
- finite state
- artifact centric
- transition systems
- temporal properties
- formal specification
- knowledge based systems
- pspace complete
- ctl model update
- automated reasoning
- computation tree logic
- concurrent systems
- knowledge base
- coalition logic
- reachability analysis
- symbolic model checking
- artificial intelligence
- binary decision diagrams