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A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS.

Yuanming ZhuShengchang CaiShiva KiranYang-Hang FanPo-Hsuan ChangSebastian HoyosSamuel Palermo
Published in: CICC (2020)
Keyphrases
  • levels of abstraction
  • low cost
  • high speed
  • higher level
  • power consumption
  • data flow
  • neural network
  • denoising
  • input data
  • low power
  • single chip