A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication.
Vincenzo RanaDavid AtienzaMarco D. SantambrogioDonatella SciutoGiovanni De MicheliPublished in: VLSI-SoC (Selected Papers) (2008)
Keyphrases
- multi processor
- network on chip
- packet switched
- program execution
- interconnection networks
- single processor
- shared memory
- multi core processors
- routing algorithm
- multistage
- general purpose
- low cost
- dynamic programming
- network simulator
- distributed memory
- power consumption
- parallel processors
- hardware implementation
- fault tolerant
- parallel algorithm