Abacus: a 1024 processor 8 ns SIMD array.
Michael BolotskiT. SimonC. VieriR. AmirtharajahThomas F. Knight Jr.Published in: ARVLSI (1995)
Keyphrases
- single instruction multiple data
- parallel processing
- processor array
- parallel architectures
- highly parallel
- random access memory
- massively parallel
- linear array
- parallel processors
- systolic array
- parallel algorithm
- high speed
- parallel implementation
- processing elements
- parallel architecture
- instruction set
- single processor
- floating point unit
- network simulator
- array processor
- real time
- high end
- distributed memory
- hardware implementation
- ad hoc networks
- routing protocol
- parallel computers
- memory management
- random access
- programmable logic
- mesh connected
- low cost
- database systems