VLSI Implementation of Low Power High Speed ECC Processor Using Versatile Bit Serial Multiplier.

M. Srinivasan G. M. Tamilselvan

Published in: J. Circuits Syst. Comput. (2017)

Keyphrases

low power
high speed
vlsi implementation
vlsi architecture
single chip
low density parity check
gate array
floating point
error correction
real time
frame rate
low power consumption
nm technology
hardware implementation
logic circuits
low cost
fir filters
filter bank
pattern recognition
associative memory