Design margin elimination in a near-threshold timing error masking-aware 32-bit ARM Cortex M0 in 40nm CMOS.

Hans Reyserhove Wim Dehaene

Published in: ESSCIRC (2017)

Keyphrases

nm technology
circuit design
analog to digital converter
error rate
human brain
low power
cmos technology
support vector
training set
low cost
high speed