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An Effective Approach Based on Partial Duplication for Reducing Soft Error Rate in SRAM-Based FPGA.
Baolong Guo
Guochang Zhou
Jinfu Wu
Xiang Gao
Yunyi Yan
Published in:
ECC (2) (2014)
Keyphrases
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error rate
power reduction
test set
power consumption
hardware implementation
lower error rates
low power
low cost
high speed
field programmable gate array
false discovery rate
equal error rate
training error
data transmission
pattern recognition
learning process
feature selection