A Novel Opamp and Capacitor Sharing 10 Bit 20 MS/s Low Power Pipelined ADC in 0.18µm CMOS Technology.
Greeshma RAnoop V. KB. VenkataramaniPublished in: ISVLSI (2017)
Keyphrases
- low power
- cmos technology
- analog to digital converter
- spl times
- mixed signal
- single chip
- power consumption
- high speed
- low cost
- low voltage
- image sensor
- power dissipation
- low power consumption
- flip flops
- power supply
- random access memory
- digital signal processing
- data flow
- parallel processing
- power management
- dynamic range