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Analyzing Vulnerability of Asynchronous Pipeline to Soft Errors: Leveraging Formal Verification.

Faiq Khalid LodhiSyed Rafay HasanOsman HasanFalah R. Awwad
Published in: J. Electron. Test. (2016)
Keyphrases
  • formal verification
  • model checking
  • symbolic model checking
  • bounded model checking
  • model checker
  • automated verification
  • program slicing
  • processing pipeline
  • temporal logic
  • error analysis
  • state space