Optimizing the overhead for network-on-chip routing reconfiguration in parallel multi-core platforms.
Marco BalboniFrancisco TriviñoJose FlichDavide BertozziPublished in: ISSoC (2013)
Keyphrases
- network on chip
- routing algorithm
- interconnection networks
- packet switched
- multi processor
- wireless sensor networks
- fault tolerant
- multistage
- routing protocol
- routing problem
- shortest path
- ad hoc networks
- multi core processors
- shared memory
- single processor
- multipath
- parallel processing
- parallel implementation
- network topology
- message passing
- network simulator
- parallel algorithm
- program execution
- scheduling problem