Scalable Video Coding Deblocking Filter FPGA and ASIC Implementation Using High-Level Synthesis Methodology.
Pedro P. CarballoOmar EspinoRomén NerisPedro Hernandez-FernandezTomasz SzydzikAntonio NúñezPublished in: DSD (2013)
Keyphrases
- high level synthesis
- hardware implementation
- parallel architecture
- scalable video coding
- bitstream
- bit rate
- efficient implementation
- rate distortion
- video coding
- signal processing
- bit depth
- rate adaptation
- video transmission
- video coding standard
- scalable video
- base layer
- video compression
- motion compensation
- multiresolution
- motion estimation