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Decreasing latency considering power consumption issue in silicon interposer-based network-on-chip.
Sajed Dadashi
Akram Reza
Midia Reshadi
Ahmad Khademzadeh
Published in:
J. Supercomput. (2019)
Keyphrases
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power consumption
network on chip
cmos technology
power dissipation
low power
energy efficiency
power management
data transfer
high speed
routing algorithm
low cost
low latency
single chip
data center
clock frequency
parallel processing
sensor data