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A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS.
Dirk Pfaff
Robert Abbott
Xin-Jie Wang
Shahaboddin Moazzeni
Ralph Mason
Raleigh Smith
Published in:
IEEE J. Solid State Circuits (2020)
Keyphrases
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high speed
metal oxide semiconductor
circuit design
power consumption
cmos technology
feature selection
low cost
mixed signal
wireless networks
digital content
analog vlsi
digital libraries
x ray
digital media
vlsi circuits
silicon on insulator