A 3.3-V/5-V low power TTL-to-CMOS input buffer.
Chi-Chang WangJiin-Chuan WuPublished in: IEEE J. Solid State Circuits (1998)
Keyphrases
- low power
- power consumption
- high speed
- low cost
- single chip
- cmos technology
- high power
- wireless transmission
- image sensor
- vlsi architecture
- logic circuits
- power dissipation
- cmos image sensor
- digital signal processing
- power reduction
- low power consumption
- mixed signal
- delay insensitive
- vlsi circuits
- gate array
- frame rate
- ultra low power