Reconfigurable Distributed FPGA Cluster Design for Deep Learning Accelerators.

Hans Johnson Tianyang Fang Alejandro Perez-Vicente Jafar Saniie

Published in: eIT (2023)

Keyphrases

deep learning
field programmable gate array
single chip
low cost
hardware implementation
embedded systems
reconfigurable hardware
data points
general purpose
unsupervised learning
hardware architecture
xilinx virtex
unsupervised feature learning