Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications.
Bilal I. AbdulrazzaqOmar J. IbrahimShoji KawahitoRoslina Mohd SidekSuhaidi ShafieNurul Amziah Md YunusLini LeeIzhal Abdul HalinPublished in: Sensors (2016)
Keyphrases
- low power
- high speed
- power dissipation
- single chip
- power consumption
- vlsi architecture
- low power consumption
- low cost
- cmos technology
- logic circuits
- mixed signal
- digital signal processing
- gate array
- power reduction
- ultra low power
- vlsi circuits
- nm technology
- image sensor
- cmos image sensor
- real time
- end to end delay
- high power
- wireless transmission
- delay insensitive
- design methodology
- embedded systems
- design process
- integrated circuit
- packet loss
- signal processor
- analog to digital converter