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Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory.
Andrzej Krasniewski
Published in:
FPL (2004)
Keyphrases
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embedded systems
optimization algorithm
smart camera
high speed
memory requirements
memory size
analog vlsi
real time
genetic algorithm
optimization process
constrained optimization
memory usage
parallel architectures
hardware software
reconfigurable hardware