A dynamic computational memory address architecture for systolic array CNN accelerators.

Min Tang Sheng Liu

Published in: HPCC/DSS/SmartCity/DependSys (2022)

Keyphrases

systolic array
parallel architecture
data flow
reconfigurable architecture
real time
management system
computational power
associative memory
image processing
computing platform
memory management
image segmentation
data structure
memory requirements
cellular neural networks