A pipelined architecture for partitioned DWT based lossy image compression using FPGA's.
Jörg RitterPaul MolitorPublished in: FPGA (2001)
Keyphrases
- pipelined architecture
- lossy compression
- discrete wavelet transform
- field programmable gate array
- hardware implementation
- multiresolution
- image quality
- image watermarking
- wavelet transform
- lossless compression
- data compression
- image compression
- subband
- wavelet domain
- low frequency
- jpeg compression
- data hiding
- embedded systems
- compression ratio
- high frequency
- wavelet coefficients
- bit rate
- signal processing
- hardware design
- image processing
- image processing algorithms
- parallel computing
- watermarking algorithm
- pattern recognition
- case study