A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-μm CMOS.
Jonathan E. RogersJohn R. LongPublished in: IEEE J. Solid State Circuits (2002)
Keyphrases
- high speed
- power consumption
- analog vlsi
- low cost
- low power
- vlsi circuits
- power supply
- delay insensitive
- single chip
- neural network
- information systems
- circuit design
- cmos image sensor
- data sets
- focal plane
- image sensor
- parallel processing
- image processing
- e learning
- artificial intelligence
- genetic algorithm
- data mining