An address generator approach to the hardware implementation of a scalable Pease FFT core.
Agenor PoloManuel JimenezDavid MarquezDomingo RodríguezPublished in: MWSCAS (2012)
Keyphrases
- hardware implementation
- signal processing
- efficient implementation
- software implementation
- pipeline architecture
- dedicated hardware
- hardware architecture
- hardware design
- image processing algorithms
- fourier transform
- fpga implementation
- frequency domain
- fpga device
- image processing
- field programmable gate array
- machine learning
- processing elements
- fpga technology
- fast fourier transform
- memory management
- shift register