A High-Performance Low Complexity All-Digital Fractional Clock Multiplier.

Nahla T. Abou-El-Kheir Ralph D. Mason Mingze Li Mustapha C. E. Yagoub

Published in: A-SSCC (2019)

Keyphrases

low complexity
motion estimation
computational complexity
lower complexity
vlsi architecture
wireless video
video encoding
high speed
video streaming
distributed video coding
multiple description coding
digital video
bit plane
high data rate
power consumption
video encoder