Hardware implementation of a high speed self-synchronizing cipher mode.
Yuanchi TianHoward M. HeysPublished in: CCECE (2015)
Keyphrases
- hardware implementation
- high speed
- efficient implementation
- software implementation
- signal processing
- dedicated hardware
- fpga implementation
- low power
- hardware architecture
- field programmable gate array
- hardware design
- real time
- image processing algorithms
- pipeline architecture
- parallel architecture
- operating system
- software development
- mode decision
- multiresolution
- pattern recognition
- fpga device
- image binarization
- shift register
- image processing