Login / Signup

ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for Low-Bit DNN Training.

Sung-En ChangGeng YuanAlec LuMengshu SunYanyu LiXiaolong MaZhengang LiYanyue XieMinghai QinXue LinZhenman FangYanzhi Wang
Published in: DATE (2023)
Keyphrases
  • artificial neural networks
  • real time
  • design process
  • training process
  • case study
  • hardware design
  • control unit
  • low power consumption
  • analog to digital converter
  • single chip
  • bit vector
  • magnetic tape