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Efficient Memory Copy Operations on the 48-core Intel SCC Processor.
Michiel W. van Tol
Roy Bakker
Merijn Verstraaten
Clemens Grelck
Chris R. Jesshope
Published in:
MARC Symposium (2011)
Keyphrases
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limited memory
memory hierarchy
high speed
cost effective
parallel processing
computing power
parallel architectures