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A 103 fJ/b/dB, 10-26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement.

Yao-Chia LiuWei-Zen ChenYuan-Sheng LeeYu-Hsiang ChenShawn MingYing-Hsi Lin
Published in: IEEE J. Solid State Circuits (2023)
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