A novel, high-speed, reconfigurable demapper-symbol deinterleaver architecture for DVB-T.
László HorváthImed Ben DhaouHannu TenhunenJouni IsoahoPublished in: ISCAS (4) (1999)
Keyphrases
- high speed
- real time
- hardware implementation
- systolic array
- high speed networks
- low power
- network architecture
- heterogeneous computing
- software architecture
- low cost
- general purpose
- digital video
- wireless channels
- reconfigurable hardware
- symbol recognition
- management system
- reconfigurable architecture
- neural network