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Design of a low power SoC testchip for wearables and IoTs.
May Wu
Ravi Iyer
Yatin Hoskote
Steven Zhang
Julio Zamora-Esquivel
German Fabila Garcia
Ilya Klotchkov
Mukesh Bhartiya
Published in:
Hot Chips Symposium (2015)
Keyphrases
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low power
single chip
power consumption
low cost
logic circuits
vlsi architecture
low power consumption
high speed
cmos technology
digital signal processing
mixed signal
gate array
power dissipation
high power
vlsi circuits
ultra low power
power reduction
cmos image sensor
nm technology
image processing