Basic Operations And Structure Of An FPGA Accelerator For Parallel Bit Pattern Computation.

Henry G. Dietz Paul Selegue Eberhart Ashley Rule

Published in: ICRC (2021)

Keyphrases

field programmable gate array
parallel implementation
pipelined architecture
parallel computation
neural network
parallel processing
efficient implementation
parallel computing
social networks
embedded systems
compute intensive
parallel hardware
xilinx virtex