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A formal model for proving hardware timing properties and identifying timing channels.

Maoyuan QinXinmu WangBaolei MaoDejun MuWei Hu
Published in: Integr. (2020)
Keyphrases
  • formal model
  • low cost
  • formal models
  • security properties
  • real time
  • predicate calculus
  • neural network
  • hardware and software
  • asynchronous circuits
  • computing systems
  • circuit design