Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA.
P. Veda BhanuRahul GovindanPlava KattamuriSoumya J.Linga Reddy CenkeramaddiPublished in: IEEE Access (2021)
Keyphrases
- high speed
- low cost
- field programmable gate array
- signal processing
- hardware design
- hardware implementation
- real time
- real time image processing
- parallel hardware
- model validation
- fpga implementation
- hardware architecture
- topology preserving
- massively parallel
- embedded systems
- binary images
- lightweight
- multiscale
- case study