Impact of clock slope on true single phase clocked (TSPC) CMOS circuits.
Patrik LarssonChrister SvenssonPublished in: IEEE J. Solid State Circuits (1994)
Keyphrases
- single phase
- high speed
- low power
- power supply
- power consumption
- delay insensitive
- analog vlsi
- cmos technology
- vlsi circuits
- power dissipation
- input output
- control algorithm
- circuit design
- control method
- low cost
- active power filter
- pulse width modulation
- digital signal processing
- high frequency
- floating gate
- focal plane
- induction motor
- intelligent control
- dynamic model
- chip design
- wavelet transform