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Low power aware standard cells using dual rail multi threshold null convention logic methodology.
M. Suresh
A. K. Panda
J. Sudhakar
Published in:
Microprocess. Microsystems (2019)
Keyphrases
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low power
high speed
logic circuits
power consumption
low cost
single chip
delay insensitive
high power
low power consumption
vlsi architecture
wireless transmission
vlsi circuits
digital signal processing
real time
gate array
cmos technology
mixed signal