Low-power adder design techniques for noise-tolerant applications.

Ihab Nahlus Lama Shaer Ali Chehab Ayman I. Kayssi Mohammad M. Mansour

Published in: SiPS (2011)

Keyphrases

low power
logic circuits
noise tolerant
single chip
power dissipation
low cost
high speed
power consumption
vlsi architecture
low power consumption
digital signal processing
gate array
design process
cmos technology
ultra low power
noisy data
power reduction
mixed signal
nm technology
lower bound
data sets