Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block selection algorithm.
Jui-Yuan HsiehShanq-Jang RuanPublished in: ASP-DAC (2008)
Keyphrases
- low power
- selection algorithm
- cmos technology
- single chip
- high speed
- low cost
- low power consumption
- power consumption
- vlsi architecture
- nm technology
- logic circuits
- digital signal processing
- power dissipation
- power reduction
- mixed signal
- pattern recognition
- gate array
- feature subset
- parallel algorithm
- simulated annealing