A Buffered Dual-Access-Mode Scheme Designed for Low-Power Highly-Associative Caches.

Yul Chu Marven Calagos

Published in: Int. J. Embed. Real Time Commun. Syst. (2013)

Keyphrases

low power
power consumption
low cost
high speed
single chip
high power
vlsi architecture
digital signal processing
wireless transmission
vlsi circuits
logic circuits
low power consumption
image sensor
signal processing
power reduction
signal processor