Login / Signup

A process-variation compensation scheme to operate CMOS digital logic cells in deep sub-threshold region at 80mV.

Robert KappelMario AuerWolfgang PribylGünter HoferGerald Holweg
Published in: ISCAS (2013)
Keyphrases
  • circuit design
  • multi agent systems
  • low cost
  • high speed
  • process model
  • low power