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Modeling and Performance Analysis for Processor-to-Processor Communications Unit Using a 100 Mb/s Optical Token Ring.
Tohru Matsunaga
Ikuro Oyaizu
E. Uozumi
T. Hoshiko
Y. Kimura
Published in:
IPPS (1991)
Keyphrases
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high speed
computer architecture
parallel processing
single chip
communication systems
printed circuit boards
data sets
neural network
distributed memory
high end
parallel processors
single processor
instruction set
multiprocessor systems