Verification and Validation of Meta-model based Transformation from SysML to VHDL-AMS.
Jean-Marie GauthierFabrice BouquetAhmed HammadFabien PeureuxPublished in: MODELSWARD (2013)
Keyphrases
- formal methods
- safety analysis
- model checking
- modeling language
- hardware implementation
- learning algorithm
- safety critical
- meta level
- integrated circuit
- real time
- efficient implementation
- intelligent agents
- knowledge acquisition
- low cost
- circuit design
- formal verification
- model checker
- image processing
- asynchronous circuits
- verification method
- meta reasoning