Memory-Side Protection With a Capability Enforcement Co-Processor.
Leonid AzrielLukas HumbelReto AchermannAlex RichardsonMoritz HoffmannAvi MendelsonTimothy RoscoeRobert N. M. WatsonPaolo FaraboschiDejan S. MilojicicPublished in: ACM Trans. Archit. Code Optim. (2019)
Keyphrases
- memory management
- intel xeon
- memory hierarchy
- memory requirements
- memory subsystem
- high speed
- memory usage
- memory access
- processor core
- computing power
- level parallelism
- random access memory
- parallel processing
- information security
- multiprocessor systems
- shared memory multiprocessors
- parallel architectures
- single chip
- external memory
- limited memory
- computational power
- associative memory
- main memory
- multithreading
- instruction set
- privacy protection
- intellectual property rights
- direct memory access
- operating system